The semiconductor industry is moving increasingly to highly complex, System-on-Chip ('SoC') solutions. Such designs add more and more functionality on a single chip, incorporating many components that were previously off-chip peripherals. The use of SoC designs has lead to significant cost, power and size reductions in electronic systems but at the cost of ever-increasing complexity which must be managed at the design stage. The interconnection of all of the various modules which make up the SoC is becoming increasingly difficult and costly as the components on the chip become smaller and as the number of modules increases.
Silistix is applying self-timed (or asynchronous) design principles to control the flow of data between the various modules of a SoC. The global clock that is currently used in SoC designs is replaced by a self-timed communication system which reduces many of the design problems associated with a global clock. Design flexibility is also increased which reduces upgrade design time and cost. Chips designed using the Silistix's methodology are said to be Globally Asynchronous, Locally Synchronous (GALS) where each module has a local clock but inter-module communication is done asynchronously.