Seminar - Challenges and Opportunities in Semiconductor and EDAPublished: Tuesday, 22 May 2018
Challenges and Opportunities in Semiconductor and EDA by Associate Professor Christos P. Sotiriou on Wednesday 23rd May 2018 in Kilburn L.T 1.4 at 2pm Abstract: Today's complex chips are designed using complex EDA tools.
Challenges and Opportunities in Semiconductor and EDA by Associate Professor Christos P. Sotiriou on Wednesday 23rd May 2018 in Kilburn L.T 1.4 at 2pm
Today's complex chips are designed using complex EDA tools. EDA tools are absolutely necessary for solving intricate problems from the device to the chip level. Technology, Architecture Trends, Opportunities and Implementation Challenges require new methodologies, tools and algorithms which tackle new algorithmic challenges. Trends and Opportunities include the use of aggressively scaled transistors/standard-cells,3DICs, asynchronous techniques. Challenges include PVT variations, managing multi-patterning complexity, low-power/sub-VT design, as well as capacity and optimisation challenges. The talk will describe problems in the EDA space today, as well as highlight potential solutions to some of them, and discuss the synergy of EDA and semiconductor sectors.
Christos P. Sotiriou received his BEng in Computer Science and Electronics, and PhD degree in Computer Science from the University of Edinburgh, Scotland, in 2001. He is an Associate Professor at the Department of Electrical and Computer Engineering of the University of Thessaly. His research interests include design methodologies for synchronous or asynchronous digital circuits and systems, Electronic Design Automation (EDA) Algorithms, Tools and Flows for digital circuit implementation, lower-power design, reliability and Power, Performance and Area (PPA) optimisation.