Hardware/Software Techniques to Address the Memory Wall on Multi-Core Systems
- Speaker: Dr Aamer Jaleel (Intel Research, Boston)
- Host: Mikel Lujan
- 1st March 2012 at 14:15 in Lecture Theatre 1.5, Kilburn Building
Multi-core processors are commonly used to address the growing memory latency. Shared resource contention, especially the shared on-chip last-level cache (LLC), influences multi-core system performance. This talk investigates hardware and software techniques to improve shared LLC performance. Hardware can improve shared LLC performance through improved cache replacement. On the other hand, software (i.e., an operating system or hypervisor) can intelligently co-schedule jobs to minimize shared LLC contention. The first part of the talk presents RRIP, a simple high performing and practical replacement policy. The next part of the talk presents an analysis on the interactions between software scheduling and LLC replacement. We show that optimal application co-scheduling is a function of the underlying LLC replacement policy. We propose Cache Replacement and Utility-aware Scheduling (CRUISE)--a hardware/software co-designed approach for shared cache management. For 4-core and 8-core CMPs, we show that CRUISE approaches the performance of an ideal job co-scheduling policy.