Our seminar series is free and available for anyone to attend. Unless otherwise stated, seminars take place on Wednesday afternoons at 2pm in the Kilburn Building during teaching season.

If you wish to propose a seminar speaker please contact Antoniu Pop.


"Xeon Phi: a many-core architecture for high performance computing"

  • Speaker:   Dr  Roger Espasa  (Intel)
  • Host:   Mikel Lujan
  • 28th November 2012 at 14:15 in Lecture Theatre 1.4 ,Kilburn Building
In this talk we will describe the MIC architecture (branded as Xeon Phi) targeted at high performance computing. Knight's Corner, the first generation of the MIC architecture, is a cache-coherent multiprocessor-on-a-chip with over 50 cores inside the package. Each core is equipped with an advanced 512b vector unit that implements a floating point multiply-add primitive. Knight's Corner is a co-processor add-in card used for example, in high performance supercomputers. In the recent top500 supercomputing list, the Stampede system using Knight's Corner co-processors ranked #7.
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