Project description

FPGA accelerators are now offered by all major cloud service providers (Amazon F1, Microsoft Azure, Baidu, Alibaba and others). However, the way this is commonly made available to customers follows a fat FPGA-as-an-Accelerator model. Here "fat" means that a user or application allocates an FPGA exclusively and "Accelerator" refers to a mode where users run only pre-built accelerators rather than their own bitstream binaries. While this solves some FPGA hardware security aspects, this omits basic cloud principles where different users run different applications with different characteristics on the same compute substrate (e.g., a Xeon processor) such that overall utilization is optimized. For example, FPGA machine learning inference (like Project Brainwave from Microsoft) uses a cluster of chips to keep all neural network weights on-chip. This leaves the available RAM attached to the FPGAs (normally 64 GB) unused. However, in the envisioned multi-tenancy scenario, a database accelerator maybe hosted along with a neural network inference application on the same FPGA to use the RAM for table storage. To make this happen, this project will develop multi-tenancy FPGA accelerator sandboxing techniques, configuration and memory management units, as well as a scalable deployment framework (e.g., something integrated into MapReduce).

This project is aligned to a couple of our present FPGA-related research projects, including the European Union projects ECOSCALE (ecoscale.eu) and EuroEXA (euroexa.eu) as well as the project rFAS (reconfigurable FPGA Accelerator Sandboxing). Through this path, the candidate will get access to a cluster of 300 large capacity FPGA nodes for test and evaluation.

The candidate should have a first class or upper second class honours degree, or a master???s degree (or equivalent qualification), in Computer Science or Electronic Engineering. Evidence of good spoken and written English has to proven with an IELTS score (or equivalent) of 6.5 or above for students whose first language is not English and who have no degree from an English speaking university. This position is open to all qualified candidates irrespective of nationality. The ideal candidate for this project has already hardware design, FPGA and/or GPU experience.

A scholarship for this project is available as one of a number of projects at this institution. This is in competition for funding with one or more of our projects. Usually the projects which receives the best applicants will be awarded the scholarship. Early applications for this project are welcome from suitably qualified candidates worldwide. Funding may only be available to a limited set of nationalities and you should read the full department and project details for further information.