Wireless or Through Silicon Data Routing on Chip

Project description

The current and almost certainly the next generation of multiprocessor hardware relies on wired connectivity
between many core processors in a hierarchy of cores, chips, boards and racks. Currently the interconnect
between all the components is achieved using high speed serial or bus connections. We believe there are
many configurations where wireless communications will be either faster or lower in energy usage than the
existing wired connections. Clearly there will also be lots of situations where wired connectivity should be
preferred to wireless due to lower latency, higher concurrent channel utilization and noise resistance etc..

There a few existing studies of wireless networking on silicon systems The aim of this research is to investigate these existing systems and to attempt to develop tools to aid hardware
system architects in choosing suitable interconnect for proposed systems on silicon. For example, the Spinnaker system, the
school???s hardware brain simulator which currently uses chips with 20 ARM cores each to simulate massive
numbers of neural circuits could act as an initial exemplar to be studied. For example, would a 64, 128, 256 ...
core chip be more or less efficient if all or some inter-core connections and data was sent via wireless rather than through on-chip wiring?

We are very unlikely to be able to build silicon to test ideas in this field so research will use analytical and simulation technologies to assess the characteristics of competing solutions. Projects looking at simulation models as well as uses for these models will be considered.

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