Fundamentals of Computer Engineering
|Unit level:||Level 1|
|Teaching period(s):||Semester 1|
|Offered by||School of Computer Science|
|Available as a free choice unit?:||N
Additional RequirementsStudents who are not from the School of Computer Science must have permission from both Computer Science and their home School to enrol.
The main aim of this course is to give students a basic understanding of the hardware which underpins computing systems.
Further aims include:
- Introduction to basic logic and logic gates
- Partitioning of simple systems into combinatorial and sequential blocks
- To introduce basic CAD tools to aid in the design of a basic computer system
- To provide an overview of hardware description languages with particular emphasis on Verilog
- Introducing logic level implementation of a simple processor
- Discussion of how computer systems interact with memory and I/O devices
OverviewIn this course you will learn about the design of digital electronic systems from simple digital circuits to the design of a simple processor. The exercises undertaken in laboratories complement the material covered in lectures. Professional commercial software tools are used in laboratories to enter designs and simulate their behaviour.
Teaching and learning methods
22 in total, 2 per week
20 hours in total, 10 2-hour sessions
Learning outcomes are detailed on the COMP12111 course unit syllabus page on the School of Computer Science's website for current students.
- Analytical skills
- Problem solving
- Written exam - 50%
- Practical skills assessment - 50%
Course unit overview and introduction to the lab.
2.Introduction to logic
Digital signals, data representation, Boolean logic and functions, De Morgan’s theorem, logic gates, multiplexers, binary arithmetic, abstraction & hierarchy, clocks, sequential systems.
3.Computer Aided Design (CAD)
Complexity and design – the need for CAD tools, testing & simulation,
4.Hardware description languages - Verilog
Introduction to Verilog, Verilog assignments, the always block and sensitivity list, design of combinatorial and sequential circuits in Verilog.
5.Register Transfer Level (RTL) Design
The synchronous paradigm, introduction to sequential systems, RTL view of design, the register, datapath and control,
6.Finite State Machines (FSM)
Introduction to the FSM, state transition diagrams, state transition tables, implementation in Verilog.
Overview of the three-box model: CPU, Memory, I/O, processor operation, instruction execution – fetch/decode/execute – and the sequencing of actions, program counter, instruction register, condition code register.
8.The Manchester University 0 (MU0) Processor
Introduction to MU0 - instruction set and operation, arithmetic logic unit (ALU) design and critical path, design of the MU0 datapath and control.
Von Neumann and Harvard architecture, tri-state buffers and bidirectional buses, memory map, address decoding schemes – one dimensional and two-dimensional, memory architectures, address decoders.
Memory hierarchy and relationship between speed, cost and capacity, cache, SRAM, DRAM, ROM, Flash, HDD and optical storage.
11.Input and output
The I/O interface, communication and I/O devices, parallel and serial communications, polling and interrupts, implementing and servicing interrupts, direct memory access, universal serial bus (USB),
12.Examples of I/O
Examples of input peripheral, output peripheral and communications using optical fibres.
COMP12111 reading list can be found on the School of Computer Science website for current students.
Feedback methodsFeedback is provided by the automated marking of submitted work. In addition, face-to-face demonstration of submitted work is undertaken for each exercise, where a demonstrator provides one-to-one feedback on the work submitted.
- Assessment written exam - 2 hours
- Lectures - 44 hours
- Practical classes & workshops - 20 hours
- Independent study hours - 34 hours